a. Field of the Invention
The present invention pertains to tools used to analyze integrated circuits during design and failure analysis and specifically to combining multiple static timing analyses and displaying the results in a useful manner.
b. Description of the Background
Integrated circuits (IC's) are extremely complex and contain an enormous number of components or cells. As the size of these components decreases, even more components can be manufactured on a single IC. The complexity of the IC's makes debugging an IC difficult and very labor intensive. Further, the sheer number of components, sometimes in the millions, may make pinpointing a problem area an enormous task.
Static timing analysis is a common method for finding problem areas of an IC during the design phase. The circuitry is simulated to determine if it meets the desired functionality. Generally, the static timing analysis can be run for several corner cases, such as high and low temperature, high and low voltages, and various processing conditions. As a check of the performance of the design prior to fabrication, many or all of the corner cases may be run and the design adjusted until all the corner cases pass. Even though the design passes all of the corner cases, a typical design will still have some problem areas that may need to be adjusted after the IC is fabricated for the first time.
It would therefore be advantageous to provide a system and method for identifying problem areas within a design prior to releasing the design to fabrication. It would further be advantageous to provide a system and method for identifying marginal problems with circuit timing, determining potential problem areas, and displaying those components with potential problems for further testing and analysis.